Digital communications networks are important elements of today's telecommunications systems. For reliable high speed digital communications, synchronous digital networks are often used, such as the synchronous optical network ("SONET").
In a synchronous digital network, a synchronization signal--e.g. a clock signal--is embedded in the data communications stream. This synchronization signal is used by various network elements (such as central offices) to reliably receive and transmit the digital data being transmitted on the network. Because the synchronization signal is often noisy (due to various kinds of signal interference), elements along the digital communications network employ filtering circuits to "clean-up" the synchronization signal. Typically, these filtering circuits are phase-locked loop circuits.
In normal operation, a phase-locked loop circuit generates an output synchronization signal based on the transfer function of the phase-locked loop circuit and the input synchronization signal. In this "closed-loop" mode of operation, there is very little difference between the output synchronization signal and the input synchronization signal, and any changes in the input synchronization signal are quickly matched by the output synchronization signal. If, however, the input synchronization signal is lost (or jumps significantly), such as when a fault occurs, the "closed-loop" mode is exited, and a "holdover" mode is entered.
In the holdover mode, the phase-locked loop circuit will be controlled to continue to operate at the average frequency at which it was transmitting when the synchronization signal was lost. When the input synchronization signal is restored, for example when the fault has been corrected or when a new input synchronization signal from another line is coupled to the phase-locked loop, then the phase-locked loop will be placed back in the closed loop mode to allow it to generate an output synchronization signal based on the input synchronization signal.
The period of time from when the input synchronization signal is restored to when the output of the phase-locked loop locks on to the input synchronization signal is known as the holdover recovery time. Ideally, this holdover recovery time would be zero. Unfortunately, in existing systems, the holdover recovery time may be significant, often on the order of several minutes, for example, for a frequency step of 4.7 parts per million ("ppm") between the input and output synchronization signal at the time the input synchronization signal is restored.
During this period of holdover recovery, data transmission errors are possible, since the output synchronization signal of the phase-locked loop is not at the same frequency as the input synchronization signal, and large phase offsets can be introduced. Therefore, a need has arisen for a method and an apparatus for frequency locking that results in faster frequency locking than prior art systems.